1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a bottom electrode of a capacitor.
2. Description of Related Art
Dynamic random access memory (DRAM) is applied broadly in the field of integrated circuits devices, and more importantly, in the electronics industry. DRAMs with higher capacitance are necessary for the development of the industry. In order to simplify the circuit constitution and to increase the density of the device, the conventional memory cell composed of three transistors is replaced by a current memory cell which is composed of a transistor series-coupled to a capacitor.
The capacitor is used to store charges that are digital data. The more the capacitance is, the less the loss of digital data is. In addition to increasing the dielectric constant of the capacitor dielectric layer and decreasing the thickness of the capacitor dielectric layer, the area of the capacitor is increased to enhance the capacitance.
FIG. 1A is schematic, cross-sectional view of a conventional bottom electrode of a DRAM capacitor. As shown in FIG. 1, the method of manufacturing a bottom electrode 114 comprises forming a dielectric layer 106 over a substrate 100 including a dielectric layer 102 and a contact pad 104. The contact pad 104 is electrically coupled to a source/drain region (not shown) formed in the substrate 100. After that, bit lines 108 and a dielectric layer 110 are formed on the dielectric layer 106 in sequence, wherein the dielectric layer 110 fills the spaces between the bit lines 108 and covers the bit lines 108. Thereafter, a photolithography and etching process is performed to define the dielectric layers 108 and 106 and to form a node contact hole 112. The node contact hole 112 penetrates through the dielectric layers 108 and 106 and exposes a portion of the contact pad 104. Then, a polysilicon layer (not shown) is formed over the substrate 100 and fills the node contact hole 112. After that, a portion of the polysilicon layer is removed until the surface of the dielectric layer 108 is exposed and a node contact 112a is formed in the node contact hole 112. A polysilicon layer (not shown) is formed over the substrate 100. A polysilicon photolithography and etching process is performed to form a bottom electrode 114 electrically coupled to the contact pad 104 through the node contact 112a. 
Since it is difficult to control the polysilicon photolithography and etching process, polysilicon material easily remains on the surface of the dielectric layer 110, which leads to the problem of a short in the capacitor. Moreover, the cross-sectional area of the bottom electrode 114 decreases from the top of the bottom electrode 114 to the bottom of the bottom electrode 114 (as shown in FIG. 1) because the polysilicon photolithography and etching process is difficult to control. Therefore, the bottom electrode will collapse in the subsequent manufacturing process.
The invention provides a method of manufacturing a bottom electrode of a capacitor. A substrate is provided. The substrate has a contact pad formed thereon, a first dielectric layer formed on the contact pad, and a node contact penetrating through the first dielectric layer and electrically coupled to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed. The remaining fifth dielectric layer and the fourth dielectric layer are removed.
As embodied and broadly described herein, the invention provides a method of manufacturing a bottom electrode of a capacitor. Since the thickness of the fourth dielectric layer can be varied with the height of the bottom electrode, the structure of the bottom electrode is relatively firm. Therefore, the invention can overcome the problem of the bottom electrode collapsing. Incidentally, in the invention, because the trench is formed in the fourth dielectric layer before the conductive layer is formed, it is unnecessary to perform the polysilicon photolithography and etching process. Hence, the problem due to the difficult-to-control polysilicon photolithography and etching process can be overcome.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.